This invention relates to delay-locked loop (DLL) circuits. More particularly, this invention relates to DLLs with feedback compensation.
A DLL uses a variable delay line to add phase delay to an input reference clock signal before that clock signal is output from the DLL. The DLL uses a phase detector to measure the phase difference between the output of the DLL and the reference clock and to adjust the variable delay to obtain the desired phase difference, which is usually zero.
As clock speeds increase, the relative length of the delay through a DLL (in clock cycles) also increases. The shorter clock period of a high speed clock becomes a smaller fraction of the total delay through a DLL. After the variable delay of the DLL is adjusted to minimize phase errors (i.e., the difference between the desired and measured phases), multiple clock periods are often required for the adjustments to propagate completely through the DLL. During this time, incorrect phase information is collected and may be acted upon by the phase detector. This can adversely affect the accuracy and performance of the DLL.
In view of the forgoing, it would be desirable to provide feedback compensation in a DLL circuit such that the circuit does not process incorrect phase information and more quickly processes updated phase information.